Design and Optimization of a 300 MSamples/s Track and Hold Architecture for a 5-bit Flash ADC in 180nm CMOS Technology

Professor Claudio Talarico
Department of Electrical and Computer Engineering
Gonzaga University
Spokane, WA, USA
E-mail: talarico@gonzaga.edu
 

Abstract: This paper introduces the design and optimization of a Track and Hold (TH) architecture that findapplication at the front end of a fully differential 5-bit flash ADC (Analog to Digital Converter). To minimize non-linearity and charge injection the architecture relies on bootstrapping and bottom plate sampling. The circuit is implemented using a standard 180nm six-metal layer digital CMOS technology and it operates from a 1.8V supply. The sampling frequency achieved is 300 MSample/s, which is consistent with the range of applications sought for the ADC. The design has been validated through simulation. The errors between analytical derivations and simulations are within 10%.

Short biography: Claudio Talarico is Associate Professor of Electrical and Computer Engineering at Gonzaga University. He holds a PhD degree in electrical engineering from University of Hawaii where he conducted research in the area of Embedded System-on- Chip. Before joining Gonzaga University, he worked at Eastern Washington University, University of Arizona, University of Hawaii, and in industry where he held both engineering and management positions in the area of VLSI integrated circuits. The companies he worked for include Infineon Technologies, in Sophia Antipolis, France, IKOS Systems in Cupertino, CA and Marconi Communications, in Genova, Italy.